1. Field of the Invention
The invention generally relates to the field of computer hardware design, and more particularly to a pipelined processor. Specifically, the invention relates to a pipelined processor which combines the advantage of in-situ error detection and correction, and the use of free slack time of noncritical stages. It can be used in designs of low power processor cores which can minimize the dynamic power by applying the techniques of adaptive voltage scaling (AVS).
2. Description of the Related Art
With the development of the integrated circuit manufacturing technologies, high-performance design and energy-efficient design have become synonymous (power-aware high-performance design becomes more and more important). The total power dissipation of an integrated circuit is divided into two major components: the dynamic component and the leakage component. And the dynamic component, which is proportional to clock frequency, overall capacitance and square of the supply voltage, is overriding compared to the leakage component. In order to save energy as much as possible, it is significant to scale the supply voltage as low as possible. At present, processors have different hardware and software strategies to achieve power management and different mode control to reduce its power consumption. The power management technology related to supply voltage modulation mainly includes the dynamic voltage and frequency scaling (DVFS) technology and the adaptive voltage scaling (AVS) technology.
The DVFS technology regulates a processor's operating clock frequency and supply voltage (for one specific system, the higher the clock frequency, the higher the supply voltage is) according to different application needs, so as to achieve the goal of energy saving. The common workflow of DVFS technology: first, the acquisition of the system load signals; then, the calculation of the current system load; last, the prediction of the performance needed in the next period according to the current system load. There are a variety of prediction algorithms based on the specific application and implemented with software and hardware support. The performance prediction is transformed into the form of clock frequency to regulate the processor matching the new clock frequency. So, compared to the DFVS technology realized by hardware, the one realized by software is simpler. Note that the clock frequency and the supply voltage regulation must ensure that the processor works robust.
AVS technology regulates the processor's supply voltage according to the adaptive advanced power control (APC) which can track the change of the processor's performance. APC passes the performance of the processor frequency, the temperature changes to the external power management chip by bus interfaces. Then, the external power management chip automatically adjusts supply voltage of the processor according to its performance requirements. This mechanism must ensure the applications run correctly with the maximum clock frequency and the minimum supply voltage.
Many ways are established to realize the AVS technology, for instance, delay chains can be used to simulate the critical path of a system. A periodical signal is input into the delay chain, the output of the delay chain is detected dynamically to adjust the power supply voltage and clock frequency. If the output of the delay chain is wrong, the timing is violated. This indicates that the system does not work correctly and the supply voltage should be increased, because the lower supply voltage leads to the longer delay time of all devices, which causes the setup timing violation thereby leading to wrong results of the data processing system. A safety margin of supply voltage is preset to ensure that the system can run correctly in the worst case for the system cannot judge and restore these mistakes by itself. Currently, a great deal of power management technology have this kind of supply voltage safety margin to limit the supply voltage, which results in conservative power saving. How to further reduce the dynamic power has become a bottleneck in power management technology.
Pipeline belonging to a CPU (Central Processing Unit) is an implementation technique in which multiple instructions are overlapped in execution. Today, the pipeline is a key to make processors fast. Generally, the pipeline consists of several stages which include combinational logic and stage registers to handle an instruction by several steps. For example, as shown in FIG. 1, the classical pipelined processor consists of five stages. The first one is instruction fetch (IF), at this stage, the processor fetches the instruction code from an instruction register. The second one is instruction decode (ID), at this stage, instruction delivered from IF stage was decoded. The third stage is execution (EX), at this stage, the processor executes the instruction decoded by ID stage, and the control signal from ID stage can allow ALU to do all kinds of action such as addition, subtraction and so on. The fourth stage is memory (MEM), at this stage; the processor can store data to memory or load data from memory. The last stage is write-back (WB), at this stage, the processor stores the result to a data register. This pipeline can execute different stages of five instructions in one clock cycle; each instruction will be executed step by step. So the average instruction execution time is shorten, the speed of CPU is accelerated. With the deeper pipeline, the processor executes programs faster and the higher clock frequency can be adopted.